8 Weeks
- VLSI
- Linux
- Digital Design
- Verilog
- FPGA
- C Refresher and Data Structures
- Projects
- VLSI Verification using System Verilog & UVM (with Project)
10 Weeks
- VLSI
- Linux
- Digital Design
- Verilog
- FPGA
- C Refresher and Data Structures
- Projects
- One Major Project Discussion
6 Months Industrial Training Placement Assistance
- VLSI Design (Front End)
- Linux
- Python
- Tcl/Tk
- Perl
- Digital Design + STA
- VHDL
- Verilog
- FPGA
- C & DS
- C++
- CMOS Design
- System Verilog
- UVM
- Projects
Labs Project, Exams, Competition
Labs Exercise, Project, Exams and Competition is conducted after course completion.