Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single small chip. VLSI began way back in the 1970s when complex semiconductor and communication technologies just began. The microprocessor is a VLSI device. Intel, AMD processors are very commonly used today in most of the computers. The term is no longer as common as it was once, as chips have increased in complexity from millions into billions of transistors.
Major giants who develop software tools for designing electronic systems such as printed circuit boards (PCB’s) and integrated circuits (IC’s) are well known companies like Cadence, Mentor Graphics and Synopsys. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Major companies in VLSI hardware designing are like Intel, AMD, Nvidia, ST Microelectronics etc.
There are several stages which are used in a chip manufacturing. There is a particular design flow for ASIC and FPGA chip design. They are separated in different stages in the following diagram:
The process of checking a design against certain properties Examining the design to make sure that the described properties by the designer to reflect correct behavior of the design hold under all conditions Property's Counter Examples: Input conditions making a property to fail Property coverage indicates how much of the complete design is exercised by the property.
Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the majority of time and effort in most large electronic system design projects specifically System on Chip (SOC’s). Functional verification is a part of more encompassing design verification, which, besides functional verification, considers non-functional aspects like timing, layout and power. Languages and methodologies like PSL , E, System Verilog, SystemC, Vera, OVM, UVM, VMM are used for the purpose of functional verification.
Logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates with the help of technology libraries which are generally provided by foundries. Common examples of this process include synthesis of HDLs. Most ASIC synthesis tools do that. However some tools can generate bit streams for programmable logic devices such as CPLDs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.
A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL) and is very similar to that used for an application-specific integrated circuit (ASIC). However the technology for a specific FPGA target is fixed by that FPGA. The goal of synthesis is to do area, timing and power optimizations.
The increasing speed and complexity of today’s designs implies a significant increase in the power consumption in VLSI chips. To meet this challenge, researchers have developed many different design techniques to reduce power and area. The complexity of today’s ICs, with over 100 million transistors, clocked at over 1 GHz, means manual power optimization would be hopelessly slow and all too likely to contain errors. EDA synthesis tools and methodologies are mandatory therefore.
It is a technique that is used to detect if a hardware physical behavior is faulty or not. Since it is a production fault, there is assumed to be no cure i.e. it is just a fault detection mechanism, not even a localization of the problem of the fault. That is the intended purpose of DFT.
Static Timing Analysis (STA) is one of the techniques to verify design in terms of timing. This kind of analysis does not depend on any data or logic inputs, applied at the input pins. The input to an STA tool is the routed netlist, clock definitions (or clock frequency) and external environment definitions. The STA will validate whether the design could operate at the assumed clock frequency, without any timing violations. Some of the basic timing violations are setup and hold timing violations. Timing Analysis Phase generates:
As a testimony one could check the speed of the latest available
Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of a mask set. Design rules are specific to a particular semiconductor manufacturing process or technology. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly.
For synchronized designs, data transfer between functional elements are synchronized by clock signals. There may be multiple clocks in a design which are working for different blocks. If there is a single clock then different clock frequencies for different blocks have to be attained by buffer insertion and gate sizing and any other optimization technique. Clock balancing is important for meeting the design constraints and clock tree synthesis is done after placement to achieve the performance goals.
Place and route is a stage in the design flow. As implied by the name, it is composed of two steps placement and routing. The first step, placement, involves deciding where to place the electronics components and logic elements in a generally limited amount of space. This is followed by routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process.
Tools used at the various stages
Floor planning - Floor planning takes in some of the geometrical constraints in a design. Examples of this are:
Initially, GDSII was designed as a format used to control integrated circuit photo-mask plotting. Despite its limited set of features and low data density, it became the industry conventional format for transfer of IC layout data between design tools of different vendors, all of which operated with proprietary data formats.
It was originally developed by Calma for its layout design software, "Graphic Data System" ("GDS") and "GDSII".
GDS II files are usually the final output product of the IC design cycle and are given to IC foundries for IC fabrication. Objects contained in a GDSII file are grouped by assigning numeric attributes to them including a "layer number", "datatype" or "texttype". While these attributes were designed to correspond to the "layers of material" used in manufacturing an integrated circuit, their meaning rapidly became more abstract to reflect the way that the physical layout is designed.
This flow is different from the ASIC flow. Once synthesis is done and the design has been placed and routed, floor planning is done and the bit file is generated by the tool. This generated bit file(binary file) is then loaded on to the FPGA board and hence FPGA’s output can be analyzed according to the design specification.