VLSI - Courses

What is VLSI?

Very-large-scale integration (VLSI) is the process of creating integrated circuits by combining thousands of transistors into a single small chip. VLSI began way back in the 1970s when complex semiconductor and communication technologies just began. The microprocessor is a VLSI device. Intel, AMD processors are very commonly used today in most of the computers. The term is no longer as common as it was once, as chips have increased in complexity from millions into billions of transistors.

  • As the size and complexity of digital/analog systems increase, more Electronic Design Tools (EDA) tools are introduced into the hardware design process.
  • Early simulation and primitive hardware generation tools have given way to sophisticated design entry, verification, high-level synthesis, formal verification, and automatic test pattern generation (ATPG) or hardware emulation and device programming tools.
  • Growth of design automation tools is largely due to hardware description languages (HDLs like VHDL and Verilog) and design methodologies that are based on these languages.
  • Based on these HDLs, new digital system EDA tools have been developed and are now widely used by hardware designers. The most widely used HDLs is the Verilog HDL.
  • Because of its wide acceptance in digital design industry, Verilog has become a must-know language for design engineers and students in computer-hardware-related fields.
Electronic design automation (EDA)

Major giants who develop software tools for designing electronic systems such as printed circuit boards (PCB’s) and integrated circuits (IC’s) are well known companies like Cadence, Mentor Graphics and Synopsys. The tools work together in a design flow that chip designers use to design and analyze entire semiconductor chips. Major companies in VLSI hardware designing are like Intel, AMD, Nvidia, ST Microelectronics etc.

  • Full Custom - Full-custom design is a methodology for designing integrated circuits by specifying the layout of each individual transistor and the interconnections between them.
  • Semi Custom - Alternatives to full-custom design include various forms of semi-custom design, such as the repetition of small transistor sub-circuits; one such methodology is the use of standard cell libraries(standard cell libraries are themselves designed using full-custom design techniques).
  • HDL Entry - The design which was planned as per the specification is coded in the HDL language i.e. VHDL or Verilog. These languages are responsible for the designing of the complex digital ICs.

There are several stages which are used in a chip manufacturing. There is a particular design flow for ASIC and FPGA chip design. They are separated in different stages in the following diagram:

Simulation
  • Simulation of a design is done for its validation, before a design is synthesized
  • Also called as RT level, or Pre-synthesis Simulation
  • Simulation at RTL level is accurate to the clock level
  • Simulation generates the tested data graphically using waveform editors, or through a test bench
Outputs of simulators:
Waveforms (for visual inspection)
Text or VCD dump for large designs for machine or designer processing

Formal Verification

The process of checking a design against certain properties Examining the design to make sure that the described properties by the designer to reflect correct behavior of the design hold under all conditions Property's Counter Examples: Input conditions making a property to fail Property coverage indicates how much of the complete design is exercised by the property.

Verification

Functional verification, in electronic design automation, is the task of verifying that the logic design conforms to specification. In everyday terms, functional verification attempts to answer the question "Does this proposed design do what is intended?" This is a complex task, and takes the majority of time and effort in most large electronic system design projects specifically System on Chip (SOC’s). Functional verification is a part of more encompassing design verification, which, besides functional verification, considers non-functional aspects like timing, layout and power. Languages and methodologies like PSL , E, System Verilog, SystemC, Vera, OVM, UVM, VMM are used for the purpose of functional verification.

Synthesis

Logic synthesis is a process by which an abstract form of desired circuit behavior, typically register transfer level (RTL), is turned into a design implementation in terms of logic gates with the help of technology libraries which are generally provided by foundries. Common examples of this process include synthesis of HDLs. Most ASIC synthesis tools do that. However some tools can generate bit streams for programmable logic devices such as CPLDs or FPGAs, while others target the creation of ASICs. Logic synthesis is one aspect of electronic design automation.

FPGA

A field-programmable gate array (FPGA) is an integrated circuit designed to be configured by a designer after manufacturing—hence "field-programmable". The FPGA configuration is generally specified using a hardware description language (HDL) and is very similar to that used for an application-specific integrated circuit (ASIC). However the technology for a specific FPGA target is fixed by that FPGA. The goal of synthesis is to do area, timing and power optimizations.

Power and Area analysis

The increasing speed and complexity of today’s designs implies a significant increase in the power consumption in VLSI chips. To meet this challenge, researchers have developed many different design techniques to reduce power and area. The complexity of today’s ICs, with over 100 million transistors, clocked at over 1 GHz, means manual power optimization would be hopelessly slow and all too likely to contain errors. EDA synthesis tools and methodologies are mandatory therefore.

DFT

It is a technique that is used to detect if a hardware physical behavior is faulty or not. Since it is a production fault, there is assumed to be no cure i.e. it is just a fault detection mechanism, not even a localization of the problem of the fault. That is the intended purpose of DFT.

STA

Static Timing Analysis (STA) is one of the techniques to verify design in terms of timing. This kind of analysis does not depend on any data or logic inputs, applied at the input pins. The input to an STA tool is the routed netlist, clock definitions (or clock frequency) and external environment definitions. The STA will validate whether the design could operate at the assumed clock frequency, without any timing violations. Some of the basic timing violations are setup and hold timing violations. Timing Analysis Phase generates:

  • Worst-case delays
  • Clocking speed
  • Delays from one gate to another
  • Required setup and hold times
  • Results of timing analysis appear in Tables and/or Graphs
  • These results are used by designers to decide on speed of their circuits.

As a testimony one could check the speed of the latest available

  • Intel processors
  • AMD processors
  • NVIDIA Graphics card
  • Analog Devices and DSPs Designs
DRC

Design Rules are a series of parameters provided by semiconductor manufacturers that enable the designer to verify the correctness of a mask set. Design rules are specific to a particular semiconductor manufacturing process or technology. A design rule set specifies certain geometric and connectivity restrictions to ensure sufficient margins to account for variability in semiconductor manufacturing processes, so as to ensure that most of the parts work correctly.

CTS

For synchronized designs, data transfer between functional elements are synchronized by clock signals. There may be multiple clocks in a design which are working for different blocks. If there is a single clock then different clock frequencies for different blocks have to be attained by buffer insertion and gate sizing and any other optimization technique. Clock balancing is important for meeting the design constraints and clock tree synthesis is done after placement to achieve the performance goals.

Place & route & FLOOR Planning

Place and route is a stage in the design flow. As implied by the name, it is composed of two steps placement and routing. The first step, placement, involves deciding where to place the electronics components and logic elements in a generally limited amount of space. This is followed by routing, which decides the exact design of all the wires needed to connect the placed components. This step must implement all the desired connections while following the rules and limitations of the manufacturing process.

Tools used at the various stages

Floor planning - Floor planning takes in some of the geometrical constraints in a design. Examples of this are:

  • Bonding pas for off-chip connections are normally located at the circumference of the chip;
  • chip area is therefore in some cases given a minimum area in order to fit in the required number of pads;
  • areas are clustered in order to limit data paths thus frequently featuring defined structures such as cache RAM, multiplier, barrel shifter, line driver and ALU
  • purchased intellectual property blocks (IP-blocks), such as a processor core, come in predefined area blocks;
  • some IP-blocks come with legal limitations such as permitting no routing of signals directly above the block.
GDS2 > GDS (Graphic Database System)

Initially, GDSII was designed as a format used to control integrated circuit photo-mask plotting. Despite its limited set of features and low data density, it became the industry conventional format for transfer of IC layout data between design tools of different vendors, all of which operated with proprietary data formats.

It was originally developed by Calma for its layout design software, "Graphic Data System" ("GDS") and "GDSII".

GDS II files are usually the final output product of the IC design cycle and are given to IC foundries for IC fabrication. Objects contained in a GDSII file are grouped by assigning numeric attributes to them including a "layer number", "datatype" or "texttype". While these attributes were designed to correspond to the "layers of material" used in manufacturing an integrated circuit, their meaning rapidly became more abstract to reflect the way that the physical layout is designed.

FPGA flow

This flow is different from the ASIC flow. Once synthesis is done and the design has been placed and routed, floor planning is done and the bit file is generated by the tool. This generated bit file(binary file) is then loaded on to the FPGA board and hence FPGA’s output can be analyzed according to the design specification.

Linux
  • Basic Linux
    • Introduction : Other OS & Linux OS
    • Basic Linux
      • Commands
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Perl
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    • Cheat Sheet
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  • Advanced Perl
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TCL / TK
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  • TCL Fundamentals : Language Syntax
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  • All about TCL Expresson
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    • TCL Procedures
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  • Tour Of The Tk Widgets
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Basic Electronics
  • Components
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Digital Design
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    • Digital Design Flow Modeling
    • Exercises

  • Advanced Digital Design
    • Computer Architecture – RISC, CISC
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      • Synthesis
      • RTL to gate Level Synthesis Examples
      • Static Timing Analysis
      • Data Path Synthesis
      • Low Power Synthesis
      • Design for testability – DFT
    • Exercises, Exam
Verilog
  • Basic Verilog
    • Verilog Language & data types
    • Modeling Delays - specparam
    • Behavioral modeling
    • Constants – localparam, parameter, defparam
    • Functions & tasks
    • Modeling circuits using all the three modeling styles
    • Behavioral modeling – Labs, Exercises

  • Advanced Verilog
    • Advanced Behavioral modeling
    • Generate – for, if, case – verilog 2001 feature
    • System tasks
    • Compiler directives
    • File I/O
    • Switch Level Modeling
    • User Defined Primitives
    • Modeling Design Examples
VHDL
  • Basic VHDL
    • Operators
    • Concurrent Stmts. – combinational logic modeling
    • Sequential Statements
    • Assertions – Concurrent, Sequential
    • Labs, Exercises

  • Advanced VHDL
    • Postponed processes
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    • Access type, file types and I/O’s
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    • User defined attributes
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    • Disconnect specification
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    • Pragmas – IP – Protection, PSL Assertions
    • Labs, Exercises, Exam, Project
FGPA
  • Introduction to FPGA
    • Architecture differences
      • CPLD
      • FPGA
    • FPGA working
    • References
  • Basics of FPGA
    • Design flow
    • Design tricks
    • H/W components on FPGA board and their working
    • Xilinx ISE tool installation and working
    • Designing basic FPGA examples
    • Designing advanced FPGA examples
    • Burn these models on available FPGA kit
System Verilog with UM
  • System Verilog
    • Introduction and all about Verification
    • Data Types & Operators
    • Procedural Statements
    • tasks & functions
    • Hierarchy & Connectivity
  • Interfaces
  • Object Oriented Paradigm (OOPS)
    • Data hiding & encapsulation
    • External methods : extern keyword
    • Inheritance : extends , super keyword
    • Ppolymorphism
    • Parameterization
    • Classes vs. structures
  • Program & Clocking Block
  • Inter Process Communication (IPC)
    • Events
    • Semaphores
    • Mailboxes
    • Fork – join, fork – join_any, fork – join_none
  • Randomization
    • Class based randomization
    • Constraints
  • System Verilog Assertions
    • Properties & sequences
    • Assert, assume, cover directives
  • Functional Coverage
  • TLM (Transaction Level Modeling) & UVM
SystemC
  • Introduction
  • Component overview
  • Data types and operator
  • Modules
  • Communication
  • Simulation timing control
  • Simulation processes
  • Dynamic processes
  • Channels
  • Verification
CMOS Design
  • Basics of transistors
    • BJTs, MOS, Other technologies, Transistor as switch
  • Complimentary MOS
    • Good 0, good 1, Pull up, Pull down, Dynamic power dissipation, Gate realizations
  • Other implementation technologies
    • Dynamic logic, Domino Logic, Psuedo-nMOS Logic, Other families : C2MOS, ..
  • Transistor Equations
    • Vt, Ids, Vds, Eqns vs SPICE model levels
  • SPICE simulation : models and parameters
    • LEVEL param : 1, 2, .. 54, BSIM3, BSIM4
    • W, L : Relation of length and width to transfer characteristics, transistor equations
    • AS, AD, PS, PD, TOX
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    • .Model, .Param, .Subckt
    • Providing inputs : PWL
    • Characterization
    • Industrial perspective
  • Layout
    • Cross-sectional, Top-level & Collating both views
    • Stick Diagrams
    • Masks
    • Basics of lithography
  • Labs
    • INV
    • NAND2
    • NOR2
    • MODEL parameters variation
    • Dynamic logic NAND2, NOR2
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C & DS
  • Introduction to C language
  • Basic Building Blocks of C
  • Control Flow
  • Conditions –
    • If, if – else, nested if
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    • Hash tables
C++
  • C++ Language
    • Introduction to C++ & its history
    • What, Where, Why C++?
    • Technical Description of C++
    • Theory of Compiler, Linker, Preprocessor, Locator, etc.
  • Basic Programming
    • Keywords, Variables & Constants, Data Types in C++
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    • Loops and flow controls
    • Arrays, pointers, strings, union & structures, preprocessor
  • Advanced Programming (OOPS)
    • Class & objects
    • Constructor & destructors
    • Inheritance & polymorphism

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